1. Field of the Invention
The present invention relates generally to information handling systems and, more particularly, to robust booting of complex multi-rail processors in the information handling system.
2. Description of the Related Art
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users are information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes, thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems, e.g., computer, personal computer workstation, portable computer, computer server, print server, network router, network hub, network switch, storage area network disk array, RAID disk system and telecommunications switch.
An information handling system having multiprocessors may include a fault resilient boot (FRB) that provides a mechanism for automatically booting up the information handling system in the event that one or more of the processors, e.g., central processing unit (CPU), fail due to either a built-in self test (BIST) problem or power-up fault (failure) during a power-on self-test (POST), so long as there is at least one functioning processor remaining in the information handling system during a subsequent POST.
A processor voltage rail type FRB may be achieved by gating the processor's system management interrupt (SMI) input with the processor's associated “Powergood” signal. The Powergood signal indicates that the necessary operating voltages to the processor have stabilized (e.g., the voltage regulators supplying the processor are functioning properly with the correct voltage outputs to the processor voltage rails). Therefore, a processor not having correct operating voltages may be kept in a disabled condition by maintaining assertion of the associated SMI# input during what would normally be a system reset de-assertion of the SMI# input to the processor. However, this is not easily implemented because the newer technology processors have multiple power rails, e.g., three or more separate power rails. The CPU Vcore power rail may be the only rail that is specific to a particular processor, whereas the rest of the power rails may be commonly shared between the plurality of processors, e.g., VTT, Vcache for the L3 cache, etc.
When the processors share multiple common power rails, in order to ensure that all of the processor power rails are functioning properly before any of the processors begin fetching program code, a “System Powergood” may utilize AND logic to insure that all processors have properly powered-up. However, the AND logic becomes complicated when a rail to a processor is not functioning properly and thereby requires masking the Powergood signal of the processor having the faulty voltage rail.